Field of the Invention
The present invention relates to vertical field effect transistors (VFETs). More particularly, the present invention relates to an improved method of forming a VFET and the resulting VFET structure.
Description of the Related Art
Integrated circuit (IC) design decisions are often driven by device scalability, device density, manufacturing efficiency and costs. For example, size scaling of planar field effect transistors (FETs) resulted in the development of planar FETs with relatively short channel lengths and, unfortunately, the smaller channel lengths resulted in a corresponding increase in short channel effects. In response, non-planar FET technologies (e.g., fin-type FET (FINFET) technologies) were developed. A FINFET is a non-planar FET that incorporates a semiconductor fin (i.e., a relatively tall and thin, elongated, rectangular-shaped, semiconductor body) and, within the semiconductor fin, a channel region positioned laterally between source/drain regions. A gate structure is positioned adjacent to the top surface and opposing sidewalls of the semiconductor fin at the channel region. Such a FINFET exhibits two-dimensional field effects as compared to the single-dimensional field effects exhibited by a planar FET and, thus, exhibits improved gate control over the channel. It should be noted that, because the semiconductor fin is so thin, any field effects exhibited at the top surface are insignificant (i.e., negligible).
Recently, vertical field effect transistors (VFETs) have been developed that allow for increased device density (i.e., a greater number of devices within a given area). A VFET device typically includes a first source/drain region in a substrate, a semiconductor fin that extends upward from the first source/drain region, and a second source/drain region that is epitaxially grown on the top surface of the semiconductor fin. A gate structure laterally surrounds the semiconductor fin and is electrically isolated from the first source/drain region and the second source/drain region by a lower and second spacer layers, respectively. However, with device size scaling, the thickness of semiconductor fins has decreased significantly (e.g., to less than 6 nm). Furthermore, processing techniques often result in tapered semiconductor fins where the upper portion is even thinner (e.g., less than 5 nm). Unfortunately, when the surface area of the top of a semiconductor fin is so small, epitaxially growing a sufficiently large second source/drain region for a VFET can be difficult and, if the size of the second source/drain region is too small, various contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.) can occur.